1. Field of the Invention
The present invention relates in general to the field of semiconductor devices. In one aspect, the present invention relates to high voltage or electrostatic discharge (ESD) protection devices for integrated input/output circuits.
2. Description of the Related Art
Integrated circuits include various components that can be destroyed by the occurrence of overvoltages, such as electrostatic discharge (ESD) events that can occur at the input/output circuits of an integrated circuit device. To protect against such overvoltages, various ESD protection circuits have been proposed, such as diode-based ESD devices that use a rail-based ESD protection scheme, and ESD devices that use silicon controlled rectifiers (SCR) to provide a local clamping ESD protection scheme. However, these conventional ESD protection schemes fail to provide adequate ESD protection or otherwise impair device performance as the scaling trend of complementary MOSFET (CMOS) technologies continues. For example, the rail-based ESD protection devices do not provide adequate ESD protection because of voltage build-up along the ESD path, and the increase in interconnect resistance in such rail-based ESD designs can cause failures, such as oxide rupture or junction breakdown. On the other hand, while the local clamping ESD schemes reduce the pad voltage and achieve higher protection level under the same stress current, they use special ESD devices with high turn-on voltage (Von) and low leakage current. Local clamping ESD schemes also require two devices to shunt current in both directions, which is the same as the aforementioned rail-based case. As a result, there are limited advantages to be gained in terms of area and overall capacitance with such schemes. With integrated circuits having sub-picofarad capacitive budgets, it becomes increasingly difficult to design an adequate device to shunt the large amount of current in the event of ESD. These design and performance challenges are exacerbated with semiconductor-on-insulator (SOI) ESD devices because of the increased self-heating and lack of vertical ESD structures due to the presence of buried oxide underneath the thin silicon (active) layer. Prior attempts to address these deficiencies include field effect diode and double-well field effect diode designs, but their capacitance savings have not been fully realized because the same number of devices are needed as in the rail-based design due to the need for current shunting in both directions (I/O pad to power supply bus and vice versa).
Accordingly, a need exists for an improved protection device, methodology and system for integrated circuits which prevents damage caused by electrostatic discharge and addresses various problems in the art that have been discovered by the above-named inventors where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.